Electronic systems that use a high level of data bandwidth, such as in multimedia applications, may need memory devices that provide the necessary rate of data transfer and other advantages. One technology that may provide the necessary bandwidth is the Rambus technology marketed by Rambus, Inc. of Mountain View, Calif. The Rambus technology is described in U.S. Pat. Nos. 5,473,575 to Farmwald et al., 5,578,940 to Dillion et al., 5,606,717 to Farmwald et al. and 5,663,661 to Dillion et al. A device embodying the Rambus technology is an example of a packet type integrated circuit memory device, because each integrated circuit receives data and addresses in packet units in a normal mode of operation. The packet is received by the Rambus device which generates internal control signals, internal data signals, and internal address signals to carry out the corresponding operation of the packet. For example, the packet may include data, address, and control signals for a write operation.
As the demand for the above described systems increases, so may the demand for Rambus devices. The time for testing of Rambus integrated circuit memory devices may therefore become more important. Testing of the Rambus integrated circuit memory device may be performed using a direct test mode wherein a portion of the control circuitry of the Rambus integrated circuit memory device is bypassed so that the memory may be controlled and accessed directly. The pins of the Rambus integrated circuit memory device may be reassigned to facilitate the testing of the Rambus integrated circuit memory device in the direct test mode.
FIG. 1 is a table illustrating pin assignments for a Rambus integrated circuit memory device operating in normal mode and in direct test mode. For example, according to FIG. 1, pins DQA&lt;5:0&gt; are used to write/read data to/from the Rambus integrated circuit memory device in normal mode. In direct test mode the same pins are designated as TestA&lt;5:0&gt; and provide the data for writing and reading data to/from the Rambus integrated circuit memory device and a portion of the row address (RADR&lt;5:0&gt;) and a portion of the column addresses (CADR&lt;5:0&gt;) in direct test mode (i.e., the core interface signals shown in FIG. 1). Other pin designations in direct test mode may be as shown in FIG. 1.
FIG. 2 is a timing diagram that illustrates direct test mode read operations of a Rambus device according to the prior art. According to FIG. 2, when the signal applied to the TestRASB pin transitions from high to low the row address applied to the test address pins selects a word line in the memory array and a bitline is sensed. When the signal applied to be TestCASB pin transitions from high to low the column address and the column bank address CBSEL are latched to the memory array. When the signal applied to the test column addressed strobe pin TestCASB returns to the high state the data read from the memory array as RWDA and RWDB. RWDA and RWDB are output from the Rambus device synchronous with the TestClkR signal via pins TestA&lt;17:0&gt;. When the precharge bank select PBSEL applied to the pins TestA&lt;17:0&gt;, and the TestRASB signal returns to a high level the activated bank is returned to the precharged state.
FIG. 3 is a timing diagram that illustrates direct test mode write operations of a Rambus device according to the prior art. According to FIG. 3, when the signal applied to the TestRASB pin transitions from high to low the row address applied to test address pins TestA&lt;17:0&gt; is latched to the memory array and a word line of the memory array is selected. When the signal applied to the TestCASB pin transitions from high to low and the column bank address CBSEL is asserted, the data input to the test address pins TestA&lt;17:0&gt; is synchronized with the test write clock TestClkW and the data RWDA and RWDB is written to the memory array address corresponding to the row address and the column address. When the TestRASB signal returns to the high state and the precharge bank address PBSEL is applied to the test address pins TestA&lt;17:0&gt; the activated bank is returned to the precharge state.
Unfortunately, test systems designed to test other types of integrated circuit memory devices may not be able to test the Rambus technology. In view of the above, there is a need for improvements in the testing of Rambus technology.